大端和小端

2.1.101. --littleend
此选项指示编译器使用小端内存为 ARM 处理器生成代码。
在小端内存中，字的最低有效字节具有最低地址。
缺省设置
除非显式指定 --bigend，否则编译器将采用 --littleend。

2.1.14. --bigend
此选项指示编译器使用大端内存为 ARM 处理器生成代码。
ARM 体系结构定义以下两种不同的大端模式：
BE8
字节固定寻址模式（ARMv6 及更高版本）。
BE32
旧大端模式。
在链接时指定是选择 BE8 还是 BE32。
缺省设置
除非显式指定 --bigend，否则编译器将采用 --littleend。

2.1.5. --be8
此选项指定 ARMv6 字节固定寻址大端模式。
这是 ARMv6 大端映像的缺省字节寻址模式，意味着链接器反转指令的端标记，
提供已按大端模式编译/汇编的输入对象的小端代码和大端数据。
字节固定寻址模式只在支持 ARMv6 和更高版本的 ARM 处理器上可用。

2.1.6. --be32
此选项指定旧的字固定寻址大端模式，即与 ARMv6 之前的大端映像相同。 
这会生成大端代码和数据。
字固定寻址模式是所有 ARMv6 之前的大端映像的缺省模式。


ARM1156T2-S Technical Reference Manual  Revision: r0p4

Differences between BE-32 and BE-8 buses

6.5.1. Differences between BE-32 and BE-8 buses

The differences between handling Word-Invariant, or BE-32, 
and Byte-Invariant, or BE-8, data buses are:

In a BE-32, Word-Invariant, system, 
the representation of a 32-bit Word access is the same 
between a BE-32 access and a LE access to the same word address. 

However, the representation of the byte (and half-word) accesses on the bus is different.

In a BE-8, 

Byte Invariant, system the representation of a byte access is the same 
between a BE-8 access and a LE access to the same byte address. 

However, the representation of the word (and half-word) accesses on the bus is different.

In BE-32 and BE-8 implementations of big-endian access, 
the lowest byte address corresponds to the most significant byte

Table 6.4 shows:

the effect of LE, BE-8 and BE-32 accesses on a 64 bit wide bus.
the basic form that for Byte accesses, LE and BE-8 columns are the same, 
and for Word accesses LE and BE-32 columns are the same.

Note

In both the BE-8 and the BE-32 cases, 
the byte access to address 0 (the lowest address) corresponds 
to the most significant byte of the word access, 
so fitting the big-endian description.


Table 6.4. Byte lanes used for LE, BE-8 and BE-32 accesses

------------+-------+--------+--------+---------+----------+----------+---------
DataBusPins |  Byte Accesses |      Halfword Accesses      | Word Accesses
------------+-------+--------+--------+---------+----------+----------+---------
            |  BE-8 |        |                             | BE-32    |  
------------+-------+--------+--------+---------+----------+----------+---------
            |  LE   | BE-32  |  LE    |  BE-8   |  BE-32   | LE       |  BE-8   
------------+-------+--------+--------+---------+----------+----------+---------
63:56       |  A7   | A4     |  A6:MS |  A6:LS  |  A4:MS   | A4:MS    |  A4:LS  
55:48       |  A6   | A5     |  A6:LS |  A6:MS  |  A4:LS   | A4:MS-1  |  A4:LS+1  
47:40       |  A5   | A6     |  A4:MS |  A4:LS  |  A6:MS   | A4:LS+1  |  A4:MS-1  
39:32       |  A4   | A7     |  A4:LS |  A4:MS  |  A6:LS   | A4:LS    |  A4:MS  
------------+-------+--------+--------+---------+----------+----------+---------
31:24       |  A3   | A0     |  A2:MS |  A2:LS  |  A0:MS   | A0:MS    |  A0:LS  
23:16       |  A2   | A1     |  A2:LS |  A2:MS  |  A0:LS   | A0:MS-1  |  A0:LS+1  
15:8        |  A1   | A2     |  A0:MS |  A0:LS  |  A2:MS   | A0:LS+1  |  A0:MS-1  
7:0         |  A0   | A3     |  A0:LS |  A0:MS  |  A2:LS   | A0:LS    |  A0:MS  
------------+-------+--------+--------+---------+----------+----------+---------

A<Num>          Byte access to address[2:0] = Num
A<Num>:<Byte>   Byte <Byte> of Word/Half-word access to address[2:0]=Num
        MS      Most significant byte
        MS-1    Second most significant byte
        LS+1    Second least significant byte
        LS      Least significant byte


ARM7TDMI Technical Reference Manual Revision: r4p1
Home > Programmer’s Model > Memory formats
2.3. Memory formats
The ARM7TDMI processor views memory as a linear collection of bytes numbered 
in ascending order from zero. For example:

bytes zero to three hold the first stored word
bytes four to seven hold the second stored word.

The ARM7TDMI processor is bi-endian and can treat words in memory 
as being stored in either:
Little-endian.
Big-endian

Note
Little-endian is traditionally the default format for ARM processors.

The endian format of a CPU dictates where the most significant byte 
or digits must be placed in a word. 

Because numbers are calculated by the CPU starting with the least significant digits, 
little-endian numbers are already set up for the processing order.

Endian configuration has no relevance unless data is stored as words and 
then accessed in smaller sized quantities (halfwords or bytes).

2.3.1. Little-endian
In little-endian format, 

the lowest addressed byte in a word is considered the least-significant byte of the word 
and the highest addressed byte is the most significant. 

So the byte at address 0 of the memory system connects to data lines 7 through 0.

For a word-aligned address A, Figure 2.1 shows how 

the word at address A, 
the halfword at addresses A and A+2, 
and the bytes at addresses A, A+1, A+2, and A+3 

map on to each other when the core is configured as little-endian.

2.3.2. Big-endian

In big-endian format, the ARM7TDMI processor stores 

the most significant byte of a word at the lowest-numbered byte, 
and the least significant byte at the highest-numbered byte. 

So the byte at address 0 of the memory system connects to data lines 31 through 24.
For a word-aligned address A, Figure 2.2 shows how 

the word at address A, 
the halfword at addresses A and A+2, 
and the bytes at addresses A, A+1, A+2, and A+3 

map on to each other when the core is configured as big-endian.


IAR C/C++ Compiler and Assembler.

Target options 

The Target options specify target-specific features for the IAR C/C++ Compiler and Assembler.

Endian mode 
Selects the byte order for your project:

Little 

The lowest byte is stored at the lowest address in memory. 
The highest byte is the most significant; it is stored at the highest address. 

Big 

The lowest address holds the most significant byte, 
while the highest address holds the least significant byte. 

Choose between two variants of the big-endian mode:

BE8 to make data big-endian and code little-endian
BE32 to make both data and code big-endian. 



http://sd-10807.dedibox.fr/show_items-feed=01a46856a67ba7423eaf4165276e1845


ARM11 BE8 and BE32    

Date: Thursday, 08 Apr 2010 02:21

What’s difference between BE8 and BE32?

BE-32 is supported by ARM cores up to the ARM11 family (v6) 
(for example ARM7TDMI, ARM926EJ-S, ARM1136JF-S). 
It is enabled by setting a bit in the CP15 system control coprocessor.

BE-8 is supported by the ARM11 family and later 
(for example ARM1136JF-S, Cortex-R4, Cortex-A8). 
Architecture v7 cores do not support BE-32.

It is controlled by setting a bit in the CPSR.

Setting both bits is reserved (not a valid configuration).

In terms of data access:

BE-8 is byte invariant endianness
BE-32 is word invariant endianness

This is easiest to see with examples. 
I’ve starred **** the important ones:

Basic endianness:

Consider a word stored 0x11223344 where "11" is the most significant byte.

Little endian:                Big endian:     

Address 0   1   2   3         Address 0   1   2   3 
Data    44  33  22  11        Data    11  22  33  44

BE-32 and BE-8

//------------------------------------------------------------------------------
Now consider data stored like this:
//------------------------------------------------------------------------------

Address 0   1   2   3 
Data    11  22  33  44

//------------------------------------------------------------------------------
// Core in little-endian
//------------------------------------------------------------------------------
Core in little-endian mode makes word access to address 0:

LDR r0, [0]
r0 contains 0x44332211
Data loaded to register as little endian

//------------------------------------------------------------------------------
Core in little-endian mode makes byte access to address 0:
LDRB r0, [0]
r0 contains 0x00000011
Data loaded from 0

//------------------------------------------------------------------------------
Core in little-endian mode makes byte access to address 3:
LDRB r0, [3]
r0 contains 0x00000044
Data loaded from 3

//------------------------------------------------------------------------------
// Core in BE-32
//------------------------------------------------------------------------------
Core in BE-32 mode makes word access to address 0:
LDR r0, [0]
r0 contains 0x44332211
Word accesses are endianness-invariant

//------------------------------------------------------------------------------
****Core in BE-32 mode makes word access to address 0:
LDRB r0, [0]
r0 contains 0x00000044
Byte access in BE-32 reads the word as if it was stored big-endian

//------------------------------------------------------------------------------
Core in BE-32 mode makes word access to address 3:
LDRB r0, [1]
r0 contains 0x00000011
As above

//------------------------------------------------------------------------------
// Core in BE-8
//------------------------------------------------------------------------------
****Core in BE-8 mode makes word access to address 0:
LDR r0, [0]
r0 contains 0x11223344
Data loaded to register as big endian

//------------------------------------------------------------------------------
Core in BE-8 mode makes byte access to address 0:
LDRB r0, [0]
r0 contains 0x00000011
Byte at address 0 is loaded, NOT the byte at address 3

//------------------------------------------------------------------------------
Core in BE-8 mode makes byte access to address 3:
LDRB r0, [3]
r0 contains 0x00000044
Byte at address 3 is loaded.

Essentially BE-32 operates by altering the addresses of memory accesses 
when accessing subword quantities. This gives the appearances of big endian.

//------------------------------------------------------------------------------
// Word Invariant/ Byte Invariant
//------------------------------------------------------------------------------

什么是word invariant ？
就是按word去访问时，数据总线上的对应的存储区域的地址是一一对应的；

什么是byte invariant ？
就是按byte去访问时，数据总线上的对应的存储区域的地址是一一对应的；

原文链接: https://www.cnblogs.com/shangdawei/archive/2012/12/10/2811629.html

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